In the stage 1 alone. To reduce latency

In order to reduce latency and increase the fan out in both
stages some efforts are made in the proposed unfolded architecture.In this
architecture a special TSMC 90nm CMOS inverters are used. The latency of these
invered 2×1 multiplexers are half than that of teh normal multiplexers.
Addition of these multiplexers haven’t made any functionality changes in our
architecture.Since we are using the inverted multiplexers inputs should be
given vice versa. In general to increase the fan out a set of buffers and
inverters are used.Since our architecture has large number of XOR gates to perform
the inverse operation the fanout tends be more here. These methods reduces the
latency in the stage 1 alone. To reduce latency in stage 2 we are using
retiming technique where the registers are retimed to perform the same
operation with reduced latency in each unfolded levels.

HARDWARE COMPLEXITY         

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            When
compared to the existing and proposed method the hardware complexity of the
proposed ADFE design has been reduced by half than the existing irrespective of
the constellation of the QAM. Though the number of inverters and buffers
increase for higher order (for the transformation of LUT1 LUT 2
contents) the hardware complexity has been reduced by the factor of 2. The
following diagram exhibits the comparison of hardware complexity.

          Fig.5. Hardware complexity comparison graph

            The above graph
shows the comparison of hardware complexity and LUT size for larger feedback
filter by several fold.In 5G system the volume of computation will be large
which inturn requires more hardware. But our design is more complex for smaller
feedbck filter and less complex for higher order feedback filter which makes
its use efficient in the 5G system.

TIME COMPLEXITY

            Throughput is defined as the ratio of  clock rate to the processing time per sample.
In other words it is defined as the maximum production within  a given period of time.Generally in DFE the
maximum clock rate is defined based on the iteration bound, whereas the time
required to process the incoming samples depends upon the order of feedback and
feedforward filters (N and L).In the exixting system the processing time
additionaly depends upon the update time of LUT content and number ofclock
cycles in  inner loops .In our proposed
system the number of clock cycle required to update the LUT contents is
minimized.The exixting system has more computational time which is reduced in
the proposed system thereby increasing the throughput.The following graph
explains the time complexity reduction clearly.

Fig.6. Throughput VS Feedback
filter order graph

CONCLUSION

            Thus our proposed system has more benefits than the existing
system which in turn makes our architecture more effective in 5G communication.Our
proposed system reduces the hardware complexity and computational omplexity
without any trade off by the factor 2 and more for higher order systems.The
throughput is also acheived upto 2.5Gbps for 16 QAM.This makes its significant
high in 5G communication where the volume of computation will be higher.We are
working over the BER and Convergence performance of the proposed architecture
to be efficient enough without any tradeoff  with the performance of the proposed design.
Our further research and studies are to reduce the power consumption of the
architecture.

In order to reduce latency and increase the fan out in both
stages some efforts are made in the proposed unfolded architecture.In this
architecture a special TSMC 90nm CMOS inverters are used. The latency of these
invered 2×1 multiplexers are half than that of teh normal multiplexers.
Addition of these multiplexers haven’t made any functionality changes in our
architecture.Since we are using the inverted multiplexers inputs should be
given vice versa. In general to increase the fan out a set of buffers and
inverters are used.Since our architecture has large number of XOR gates to perform
the inverse operation the fanout tends be more here. These methods reduces the
latency in the stage 1 alone. To reduce latency in stage 2 we are using
retiming technique where the registers are retimed to perform the same
operation with reduced latency in each unfolded levels.

HARDWARE COMPLEXITY         

We Will Write a Custom Essay Specifically
For You For Only $13.90/page!


order now

            When
compared to the existing and proposed method the hardware complexity of the
proposed ADFE design has been reduced by half than the existing irrespective of
the constellation of the QAM. Though the number of inverters and buffers
increase for higher order (for the transformation of LUT1 LUT 2
contents) the hardware complexity has been reduced by the factor of 2. The
following diagram exhibits the comparison of hardware complexity.

          Fig.5. Hardware complexity comparison graph

            The above graph
shows the comparison of hardware complexity and LUT size for larger feedback
filter by several fold.In 5G system the volume of computation will be large
which inturn requires more hardware. But our design is more complex for smaller
feedbck filter and less complex for higher order feedback filter which makes
its use efficient in the 5G system.

TIME COMPLEXITY

            Throughput is defined as the ratio of  clock rate to the processing time per sample.
In other words it is defined as the maximum production within  a given period of time.Generally in DFE the
maximum clock rate is defined based on the iteration bound, whereas the time
required to process the incoming samples depends upon the order of feedback and
feedforward filters (N and L).In the exixting system the processing time
additionaly depends upon the update time of LUT content and number ofclock
cycles in  inner loops .In our proposed
system the number of clock cycle required to update the LUT contents is
minimized.The exixting system has more computational time which is reduced in
the proposed system thereby increasing the throughput.The following graph
explains the time complexity reduction clearly.

Fig.6. Throughput VS Feedback
filter order graph

CONCLUSION

            Thus our proposed system has more benefits than the existing
system which in turn makes our architecture more effective in 5G communication.Our
proposed system reduces the hardware complexity and computational omplexity
without any trade off by the factor 2 and more for higher order systems.The
throughput is also acheived upto 2.5Gbps for 16 QAM.This makes its significant
high in 5G communication where the volume of computation will be higher.We are
working over the BER and Convergence performance of the proposed architecture
to be efficient enough without any tradeoff  with the performance of the proposed design.
Our further research and studies are to reduce the power consumption of the
architecture.

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