Designed by intel
having 20 bit address line and 16 data lines.
Provides 1MB storage.
queue which contains 6 instruction bytes from memory
Consist of 29,000
#8086 is then divided
into two units:
instruction to BIU starting from where to fetch the data and decode and then
function is to control data operations using instruction decoder and ALU.
direct connection with system bus.
ALU- Handle arithmetical
and logical operations
16 bit register acts like flip-flop that means it changes its status acc. To
value stored in accumulator.
9 flags and basically divided into two groups:-
2. Control flags
#Represent result of last
arithmetic and logical operations.
Flag- Indicates overflow condition of arithmetic operations.
Flag- When operation performed at ALU, sometimes results in a carry, here this
flag is set.
#Main function is to perform Binary and BCD
Flag- Used to indicate the parity of result. When lower order 8 bits of result
contains even number of 1’s, then parity flag is set. If it is odd, then parity
Flag- If result of arithmetic or logical operations is zero, and then it is set
to 1 or else set to 0.
Flag- Holds sign of result. When result is negative then set to 1 or else set
Flag- Represent result when system capacity is exceeded.
2. Interrupt Flag
3. Direction Flag
General Purpose Registers:-
pair can store 16 bit data
there are 8 G.P. registers
(Accumulator Register) – Used to store operand for arithmetic operations.
(Base Register) – Store starting base address of memory area within data
(Counter Register) – Used in loop instruction to store loop counter.
(Data Register) – Used to hold I/O port address.
BIU (Bus Interface Unit) –
cares of all data and address transfer on buses for EU like sending address,
fetching instruction from memory, read and write the data from and to the ports
and BIU are connected by internal bus.
has following functional parts:-
Ø Instruction Queue –
BIU gets 6 bytes of next instruction and store them in
When EU gets ready for next instruction, then it
simply reads instruction from queue and hence resulting in increased execution speed.
# Fetching the next instruction while current
instruction executes is called pipelining.
Ø Segment Registers –
Holds the address of data and instruction in memory,
and which are used by processor to access memory location.
# contains one pointer register IP which holds the
address of next instruction to get executed by EU.
There are 4 types of Segment Registers –
(Code Segment) – Used for addressing a location in code segment of memory.
(Data Segment) – Contains data used by program and is accessed in data segment
by offset address.
(Stack Segment) – Handles memory to store data and address during execution.
(Extra Segment) – Used by string to hold extra data.
Instruction Pointer – 16 bit register which holds address of next instruction
to be executed.